The non-volatile memory which can write and erase data electrically has been well known as flash type EEPROM. In the flash type EEPROM, memory cells of double layer structure having a floating gate are used. That is, when data are required to be written, hot electrons are injected into the floating gates; and when data are required to be erased, a high supply voltage is applied to the sources of the MOS transistors for constituting the memory cells, respectively.
The structure and principle of the memory cells of the flash type EEPROM as described above are disclosed in Intel Flash Memory/28F256A, 28F512, 28F010, 28F20, Intel Corp. Engineering Report ER24, October 1991, for instance.
In general, the above-mentioned flash type EEPROM is provided with such a function as to erase data in all the chip and data in unit of block, respectively. In addition, the flash type EEPROM usually has a verify function for confirming whether the data in the memory cells have been completely erased or not after erasure operation.
FIG. 20 is a block diagram showing a memory construction of a conventional non-volatile semiconductor memory device, in which the structure provided with erase and verify functions in unit of block are shown in particular.
As shown, a cell array 1 is constructed being divided into several array blocks 1 to 8. To the cell array 1, word select lines WL1 to WLn are connected. These word select lines WL1 to WLn are derived from a row decoder circuit 6. On the basis of decoding operation of the row decoder circuit 6, only one of the word select lines WL1 to WLn is activated to select one word line of the memory cell array 1. On the other hand, bit lines are derived from a column gate transistors group 7, and 4-bit lines are selected on the basis of a decode signal outputted by a column decoder circuit 15.
Through the bit lines selectively derived via the column gate transistor group 7, data are written in and read from the cell array 1. That is, data are written in the cell array 1 through a write load circuit 16 and read from the cell array 1 through a sense amplifier 8 composed of 4 sense amplifier blocks S/A1 to S/A4.
An input/output circuit 9 inputs commands and data, and further outputs data. The commands and data are inputted or outputted as 4 bit data. When data inputs Din1 to Din4 inputted to the input/output circuit 9 are data, these data are written in the memory cell array 1 through the data write load circuit 16. When data inputs Din1 to Din4 inputted to the input/output circuit 9 are commands, these command data are given to a command input circuit 12. The cell array (1) data read through the sense amplifier 8 are outputted to the outside through the input/output circuit as 4 bit read data D*1 to D*4. Further, the read data D*1 to D*4 are given to a verify circuit 11 to verify erasure results in unit of chip or block.
The addresses A0 to An for selecting memory cells in the cell array 1 are inputted through an address buffer circuit 5. When an internal signal C is at an "L" level, the address buffer circuit 5 outputs the addresses A0 to An, as they are, as A*0 to A*n; and when the internal signal C is at an "H" level, the address buffer circuit 5 outputs an output of a counter circuit 10 as the address A*0 to A*n. The addresses A*0 to A*n include both column addresses A*0 to A*3 and row addresses A*6 to A*n, respectively,
The addresses A*0 to A*2 in the column addresses A*0 to A*3 are applied to both the column decoder circuit 15 and a block decoder 3 through an address latch circuit 4 as addresses AL*0 to A*L2. The address A*3 of the column addresses A*0 to A*3 is directly applied to the column decoder circuit 15.
Here, when an internal signal A is at the "L" level, the address latch circuit 4 outputs the column addresses A*0 to A*2, as they are, as the addresses AL*0 to AL*2. However, when the internal signal A changes to the "H" level, the address latch circuit 4 latches the column addresses A*0 to A*2 at a time point when the internal signal A changes to the "H" level, and outputs the latched addresses, as the addresses AL*0 to AL*2.
When an internal signal B is at the "L" level, the block decoder 3 decodes the addresses AL*0 to AL*2 and outputs any one of the block select signals EA1 to EA8 as the "H" level signal. When the internal signal B is at the "H" level, the block outputs all the block select signals EA1 to EA8 as the "H" level signals. These block select signals EA1 to EA8 are given to cell source voltage supply blocks CSC1 to CSC8 of a cell source voltage supply circuit 2 to erase data in the cell array 1 in unit of chip or block.
On the other hand, the row addresses A*6 to A*n of the addresses A*0 to A*n given by the address buffer circuit 5 are decoded by the row decoder 6 and then given to the cell array 1 thorough the word select lines WL1 to WLn. Here, when the internal signal C is at the "L" level, the row decoder circuit 6 decodes the given addresses; and when the internal signal C is at the "H" level, the row decoder circuit 6 deactivates all the word select lines WL1 to WLn.
Further, the column address A*3 and the addresses AL*0 to AL*2 of the address latch circuit (of the addresses A*0 to A*n) are all inputted to the column decoder circuit 15, and the decoded signals are given to the column gate transistor group 7. Further, the decoded signals are used to derive bit lines from the column gate transistor group 7, for column selection of the respective cell array blocks 1 to 8 of the cell array 1. Here, when the internal signal C is at the "L" level, the column decoder circuit 15 decodes the addresses. When the internal signal C is at the "H" level, however, the column decoder circuit 15 does not derive the bit lines from the column gate transistor group 7.
Now, to the respective cell array blocks 1 to 8, the cell source voltage supply blocks CSC1 to CSC8 for supplying an erase voltage to the sources of the MOS transistors for constituting the cell array 1 in unit of block are connected for data erasure. These cell source voltage supply blocks CSC1 to CSC8 constitute a cell source voltage supply circuit 2. On the basis of block select signals EA1 to EA8 applied from the block decoder 3, the cell source voltage supply circuit 2 controls the erasure operation in unit of chip or block by selecting none, one or all of the cell source voltage supply blocks CSC1 to CSC8.
A read/write control circuit 14 controls data write and data read in and from the cell array 1 through the input output circuit 9, and further data erasure from the cell array 1 through an automatic erase control circuit 13. To the read/write control circuit 14, a CE signal, an OE signal and an external voltage Vpp are inputted.
When data in the cell array 1 are erased, the read/write control circuit 14 outputs a control signal CME to the command input circuit according to the commands (i.e., data input Din1 to Din4) inputted through the input/output circuit 9. In response to the control signal CME, the command input circuit 12 outputs the internal signal A or B. On the basis of the internal signal A or B of the command input circuit 12 and the signal applied by the read/write control circuit 14, the automatic erase control circuit 13 outputs the internal signal C or D and further controls the counter circuit 10.
When all the data D*1 to D*4 outputted by the sense amplifier 8 for reading data from the cell array 1 are at the "H" level, the verify circuit 11 checks the erasure statuses (levels) of the cell array (1) data read by the sense amplifier 8, and gives the checked result to the counter circuit 10 as a verify signal VRF. Further, the operation of the verify circuit 11 is controlled on the basis of the internal signal D applied by the automatic erase control circuit 13.
In the erasure operation, the automatic erase control circuit 13 controls the counter circuit 10 to generate erase addresses, disables the addresses A0 to An inputted to the address buffer circuit 5, and gives the internal signal C to the row decoder circuit 6 and the column decoder circuit 15 to deactivate the output lines thereof. In accompany with the erasure operation, at the same time, the automatic erase control circuit 13 gives the internal signal C to the cell source voltage supply circuit 2 to active the circuit 2 and the internal signal D to the verify circuit 11 to disable the verify signal VRF outputted by the verify circuit 11.
FIG. 21 is a block diagram showing only the cell array 1, the sense amplifier 8 and the write load circuit 16 all extracted from the conventional memory device shown in FIG. 20. As shown in FIG. 21, the cell array blocks 1 to 8 for constituting the cell array 1 are each composed of MOS transistors arranged into a matrix pattern. The word select lines WL1 to WLn are connected to the gates of the respective MOS transistors in unit of word. Further, the source lines of the respective MOS transistors are connected in common to one CSC1 of the cell source voltage supply blocks CSC1 to CSC8 of the cell source voltage supply circuit 2 shown in FIG. 20, respectively in unit of cell block.
Further, the drains of the transistors for constituting the cell block are derived as bit lines and connected to the sense amplifier 8 and the write load circuit 16 via two MOS transistors 20 and 19 for constituting the column gate transistor group 7 shown in FIG. 20.
Further, to the gates of the transistors 19 for constituting the column gate transistor group 7, signals g1 to g8 are given from the column decoder circuit 15 shown in FIG. 20, respectively. On the other hand, to the gates of the transistors 20 for constituting the column gate transistor group 7, signals h1 and h2 are given from the column decoder circuit 15 shown in FIG. 20, respectively.
In the circuit construction as described above, one of the rows of the cell array 1 (one of the word select lines WL1 to WLn) is selected on the basis of a row address, and the four columns thereof are selected by the transistors 19 and 20 of the column gate transistor group 7.
In data write, the four bit lines selected on the basis of the cell selection are connected to the selected memory cells to write 4-bit data inputs Din1 to Din4 given from the write load circuit 16 in the selected memory cells. In data read, on the other hand, the selected memory cells are connected to the sense amplifier 8 to read internal data D*1 to D*4.
FIG. 22 is a circuit diagram showing the row decoder circuit 6 and the column decoder circuit 15 shown in FIG. 20, in which the row addresses A*6 to A*n are denoted by A*i (i=6 to n). Further, inversion signals of the row addresses A*i are denoted by inversion row addresses/A*i. All the combinations of the row addresses A*i and the inversion row addresses/A*i are inputted to NAND gates 17. On the other hand, an inversion signal of the internal signal C is applied to the NAND gates 17 via an inverter 31, respectively.
The outputs of the NAND gates 17 are connected to the word select lines WL1 to WLn via a MOS transistor 21 and an inverter circuit 22, respectively. The transistor 23 is used to pull up the gate of the inverter circuit 22 to the external voltage Vpp or the supply voltage Vcc. Further, the external voltage Vpp and the supply voltage Vcc are both applied also to the inverter 22, respectively.
On the other hand, the column addresses A*3 and AL*0 to AL*2 are denoted by the column addresses A*j (j=0 to 3). The inversion signals of the column addresses A*j are denoted by inversion column addresses/A*j. All the combinations of the column addresses A*j and the inversion column addresses/A*j are inputted to NAND gates 18. On the other hand, an inversion signal of the internal signal C is applied to the NAND gates 18 via the inverter 31, respectively.
The outputs of the NAND gates 18 are outputted as signals g1 to g8 (or h1 or h2) through a MOS transistor 25 and an inverter circuit 24, respectively. The transistor 26 is used to pull up the gate of the inverter circuit 24 to the external voltage Vpp or the supply voltage Vcc. Further, the external voltage Vpp and the supply voltage Vcc are both applied also to the inverter 24, respectively.
In data write, a high voltage of 12 V obtained by applying the external voltage Vpp to the inverter circuit 22 is applied to the selected one of the word select lines WL1 to WLn. On the other hand, a high voltage of 7 V is applied to the selected bit lines from the write load circuit 16. As a result, 4 bit data can be written in the memory cells selected by the row decoder circuit 6 and the column decoder circuit 15.
In data read, on the other hand, the supply voltage Vcc is applied to the inverter circuit 22 of the selected one of the word select lines WL1 to WLn. Data of the selected bit lines are sensed by the sense amplifier 8 and read as 4 bit internal data D*1 to D*4.
FIG. 23 is a detailed circuit diagram showing the address latch circuit 4 shown in FIG. 20, in which the addresses A*0 to A*2 are denoted by address A*i (i=0 to 2). Further, the addresses AL*0 to AL*2 are denoted by address AL*i. The address A*i is inputted to a switched inverter 27 through an inverter 32. On the other hand, the internal signal A is inputted to the switched inverter 27 and a switched inverter 28 directly or after inverted through an inverter 33. Under control of the internal signal A, the switched inverter 27 outputs an inversion output of the inverter 32 when the signal A is at the "L" level, and sets its output to a high impedance when at the "H" level. The output of the switched inverter 27 is given to the inverter 34 and the switched inverter 28.
The output of the inverter 34 is inverted through the inverter 35 and then outputted as an address AL*i. Further, the input of the inverter 35, that is, the output of the inverter 34 is returned to the input of the inverter 34 through the switched inverter 28. The switched inverter 28 sets its output to a high impedance when the internal signal A is at the "L" level, but outputs its inverted input when at the "H" level. In other words, when the internal signal is at the "H" level, the switched inverter 28 and the inverter 34 both have a self-holding function. Here, the output of the inverter 34 is outputted as an inversion address/AL*i.
In the above-mentioned circuit construction, the address latch circuit 4 outputs an address A*i, as it is, as an address AL*i and an inversion address/AL*i when the internal signal A is at the "L" level, but holds the address A*i immediately before the internal signal A changed to the "H" level by the switched inverter 28 and then outputs the held address AL*i and the held inversion address/AL*i when the internal signal A changes to the "H" level.
FIG. 24 is a circuit diagram showing the block decoder 3 shown in FIG. 20. In the same way as in FIG. 24, all the combinations of the addresses AL*i and the inversion addresses/AL*i are inputted to NAND gates 29, respectively. The outputs of the NAND gates 29 are inputted to NAND gates 30, respectively together with the internal signal B inputted through an inverter 36.
In other words, the addresses AL*i and the inversion addresses/AL*i are decoded by the NAND gates 29, and the decoded results are outputted through the NAND gates 30. When the internal signal B is at the "L" level, the outputs of the NAND gates 30 are enabled to the "L" level. When the internal signal B is at the "H" level, however, the block select signals EA1 to EA8 are all fixed at the "H" level.
FIG. 25 is a circuit diagram showing one of the cell source voltage supply blocks CSC1 to CSC8 for constituting the cell source voltage supply circuit 2 shown in FIG. 20, in which the block select signals EA1 to EA8 are inputted to a NAND gate 37 together with the internal signal C as block select signal EAi (i=1 to 8). The output of the NAND gate 37 is inputted to the gates of transistors 38 and 45 and further to an inverter 42. The output of the inverter 42 is connected to the gate of a transistor 39. The drain of the transistor 38 is connected to the drain of a transistor 40 (whose source is connected to an external voltage Vpp) and to the gate of a transistor 41 (whose source is connected to the external voltage Vpp). The drain of the transistor 39 is connected to the gate of the transistor 40 and the drain of the transistor 41. Further, the drain of the transistor 41 is connected to the gate of a transistor 44 connected to the drain of the transistor 45. The source of the transistor 44 is connected to the source of the transistor 43 having a gate to which an UHE of 15 V is inputted and a drain to which the external voltage Vpp is connected.
When the block select signal EAi and the internal signal C are both not at the "H" level, the output of the NAND gate 37 is at the "H" level, and the output of the inverter 42 is at the "L" level. As a result, the transistors 38 and 45 are both turned on, and the transistor 39 is turned off. When the transistor 38 is turned on, since the transistor 41 is turned on, the external voltage Vpp is given to the gate of the transistor 44. Therefore, the transistor 44 is turned off, so that the voltage applied from the cell source voltage supply block CSCi to the cell source line of the cell block i becomes zero. Further, since the drain voltage of the transistor 41 is also given to the gate of the transistor 40, the transistor 40 is kept turned off.
On the other hand, when the block select signal EAi and the internal signal C are both at the "H" level, the output of the NAND gate 37 is at the "L" level and the output of the inverter 42 is at the "H" level. As a result, the transistors 38 and 45 are both turned off and the transistor 39 is turned off. Here, when the transistor 38 is turned off and the transistor 39 is turned on, the transistor 41 is turned off and the transistor 40 is turned on. When the transistor 40 is turned on, since the gate of the transistor 44 changes to the "L" level, the transistor 44 is turned on, so that the external voltage Vpp is outputted to the drain of the transistor 44 from the source of the transistor 43 through the transistor 44. Accordingly, the voltage applied from the cell source voltage supply block CSCi to the cell source line of the cell array block i becomes the external voltage Vpp, that is, a high voltage of 15 V for erasure operation.
FIGS. 26A and 26B are circuit diagrams showing the command input circuit 12 shown in FIG. 20. In FIGS. 26A and 26B, the data inputs Din1 to Din4 are inputted to a NAND gate 46. The output of the NAND gate 46 is outputted as the internal signal A through switching gates 47, 48, 49 and 50, to each of which a control signal CME is applied directly and via an inverter 51. Here, the respective inputs of the switch gates 48 and 50 are connected to a transistor 66 having a gate to which a reset signal RST is applied. The drain of the transistor 66 is connected to the switching gate 49 through a series circuit composed of inverters 52 and 53 and further to the output side of the transistor 50 via a series circuit composed of inverters 54 and 55.
In the above-mentioned system, when the bits of data inputs Din1 to Din4 are all at "1", that is, when the command data is "F", the internal signal A is to be outputted.
On the other hand, the data input Din1 is inverted by an inverter 68 and then inputted to a NAND gate 56. The data inputs Din 2 to Din4 are directly inputted to the NAND gate 56. The output of the NAND gate 56 is outputted as the internal signal B through switching gates 57, 58, 59 and 60 to each of which a control signal CME is applied directly and via an inverter 61. Here, the respective inputs of the switch gates 58 and 60 are connected to a transistor 67 having a gate to which a reset signal RST is applied. The drain of the transistor 67 is connected to the switching gate 59 through a series circuit composed of inverters 62 and 63 and further to the output side of the transistor 60 via a series circuit composed of inverters 64 and 65.
In the above-mentioned system, when the data inputs Din1 is at "0" and Din2 to Din4 are at "1", that is, when the command data is "E", the internal signal B is to be outputted.
Here, the internal signal A corresponding to the command data "F" corresponds to block erasure mode, and the internal signal B corresponding to the command data "E" corresponds to chip erasure mode.
FIG. 27 is a circuit diagram showing the verify circuit shown in FIG. 20. In FIG. 27, NAND gates 69 and 70A constitute a circuit for detecting all "1" of the internal data D*1 to D*4. Therefore, when the internal data D*1 to D*4 are all at "1" and further the internal signal D inputted to an inverter 72A is at "1", the inputs of a NOR circuit 71A are all set to "0", so that a verify signal VRF of "1" is outputted from the NOR circuit 71A.
The operation of the circuits shown in FIGS. 20 to 27 will be described hereinbelow with reference to FIGS. 28 to 31.
Addresses A0 to An for accessing the cell array 1 are given from the outside to the address buffer circuit 5. In the normal operation, that is, when the internal signal C is not outputted, the addresses A0 to An are given to the inside as addresses A*0 to A*n.
The addresses A*0 to A*2 of the column addresses A*0 to A*3 in the addresses A0 to An are given to the address latch circuit 4. In the normal operation, however, since the internal signal A is not outputted, the addresses are outputted as addresses AL*0 to AL*2, as they are as.
These addresses AL*0 to AL*2 are given to the block decoder 3, decoded when the internal signal B is not outputted, and then given to the cell source voltage supply circuit 2 as the block select signals EA1 to EA8. In the normal operation, however, since the internal signal C is not outputted, the operation of the cell source voltage supply circuit 2 is kept locked.
The row addresses A*6 to A*n of the addresses A*0 to A*n are given to the row decoder 6. In the normal operation, since the internal signal C is not outputted, these addresses are decoded as they are, and then given to the cell array 1 through the word select lines WL1 to WLn as a row select signal. As a result, a word select line WL can be selected in the cell array 1.
Further, with respect to the column addresses A*0 to A*3 of the addresses A*0 to A*n, the column address A*3 is directly given to the column decoder circuit 15, and the column addresses AL*0 to AL*2 are given to the column decoder circuit 15 via the address latch circuit 4 as the addresses AL*0 to AL*2. In the normal operation, since the internal signal C is not outputted, these addresses are decoded as they are, and then given to the column gate transistor group 7 as the column select signals. As a result, 4 bit lines of the word select lines are selected in the cell array 1, and the selected bit lines are connected to the sense amplifier 8 and the write load circuit 16.
As described above, the specific cells of the cell array 1 are selected and connected to the sense amplifier 8 and the write load circuit 16. That is, data are written in the selected cells through the write load circuit 16, and data are read from the selected cells through the sense amplifier 8.
In the data write, the data inputs given to the input/output circuit 9 are given to the write load circuit 16 as the data inputs Din1 to Din4 to activate the selected bit lines, so that the data inputs Din1 to Din4 are written in the selected cells of the cell array 1.
On the other hand, the levels of the bit lines connected to the selected cells of the cell array 1 are read by the sense amplifier 8, and then given to the input/output circuit 9 as the data D*1 to D*4, so that the data are outputted to the outside as the data output.
The above-mentioned data write and read operation is controlled by the read/write control circuit 14.
Now, in the non-volatile semiconductor memory device as described above, when data in the cell array 1 are erased, it is possible to select any one of chip erasure mode and block erasure mode.
First, the operation of when all the bits of the chip are erased will be described hereinbelow with reference to a flowchart shown in FIG. 28 and a timing chart shown in FIG. 29. Here, in FIG. 29, (a) denotes the external voltage Vpp; (b) denotes the external OE signal; (c) denotes the control signal CME; (d) denotes the external CE signal; (e) denotes the timing at which data inputs Din1 to Din4 are inputted as commands; (f) denotes the statuses (levels) of the data inputs Din1 to Din4; (g) denotes the internal signal A; (h) denotes the internal signal B; (i) denotes the internal signal C; (j) denotes the internal signal D; (k) denotes the verify signal VRF; (1) denotes the address A*0; (m) denotes the address A*1; (n) denotes the address A*n; (o) denotes the word select line WL1; (p) denotes the word select line WLn; (q) denotes the column decode signal g1; (r) denotes the column decode signal (s) denotes the column decode signal g8; (t) denotes the column decode signal h1; (u) denotes the column decode signal h2; and (v) denotes all the cell source line voltages of the cell array 1, respectively.
First, at time t1, simultaneously when the external voltage Vpp rises up to 12.5 V as shown by (a) in FIG. 29, the external OE signal changes to the "H" level as shown by (b). As a result, the control signal CME of the read/write control circuit 14 changes to the "H" level as shown by (c). Then, command data are fed to the data inputs Din1 to Din4 of the input/output circuit 9 as shown by (e). In the case of the chip erasure, as shown by (e), these command data are "E".
With respect to the processing procedure, in step S1, the command data "E" are inputted, and then control (i.e., the processing) proceeds to step S2 to start erasure operation.
Then, as shown by (d) in FIG. 29, the external signal CE is inputted as a negative signal. When the external CE signal rises at time t2, the command data "E" are latched by the command input circuit 12, so that the internal signals B and C outputted by the command input circuit 12 change to the "H" level as shown by (h) and (i) to start erasure period in step S2. In this case, all the block select signals EA1 to EA8 extending from the block decoder 3 change to the "H" level on the basis of the internal signal B. At the same time, in step S3, the counter circuit 10 is set by the automatic erase control circuit 13.
As a result, in step S4, the internal addresses A*0 to A*n are set to "0", and further the outputs of the row decoder circuit 6 and the column decoder circuit 15 are set to the non-select status on the basis of the internal signal C, respectively.
Further, on the basis of the internal signal C, since 12 V is applied to all the cell source lines of the cell array 1 through the cell source voltage supply circuit 2 as shown by (v) in FIG. 29, in step S5 all the cell blocks 1 to 8 of the cell array 1 are erased. In this case, the erasure period is about 10 ms as shown by (i) in FIG. 29. In this erasure operation, since the cell source line voltages of all the cell array blocks 1 to 8 of the cell array 1 are set to 12 V by the external voltage Vpp, electrons are extracted from the floating gates of the memory cells, so that the cells can be erased.
When the erasure period ends at time t3, the internal signal C returns to the "L" level as shown by (i) in FIG. 29, and the internal signal D returns to the "H" level as shown by (j) in FIG. 29, so that the verify period starts. In this period, in step S6, the cell source voltage applied by the cell source voltage supply circuit 2 is zeroed to stop erasure operation.
In the verify period, the internal addresses A*0 to A*n are advanced by the counter circuit 10 to execute the verify operation in step S7 and the data "1" check in step S8. Beginning from the first address of the chip, the addresses A*0 to A*n are checked in sequence as shown by (1), (m) and (n) in FIG. 29. As a result, the word select lines WL1 to WLn change as shown by (o) and (p), and the column decode signals g1 to g8 and h1 and h2 change in sequence as shown by (q), (r), (s), (t) and (u) in FIG. 29. In correspondence to the above-mentioned address change, cell data in the respective cell array 1 are read. After the data have been erased completely, the data D*1 to D*4 read through the sense amplifier 8 are all at "1". In other words, as far as the data are erased completely, as shown by (k) in FIG. 29, the verify signal VRF is outputted by the verify circuit 11 to the counter circuit 10. Here, if the address is not the final address in step S10, control proceeds from step S10 to step S9 to increment the count value of the counter circuit 10, so that the address is advanced by 1. As a result, data at the succeeding address are read through the sense amplifier 8, and the read data are also verified.
Now, as the result of the final address check in step S10, if the erasure is not sufficient, the verify circuit 11 does not output the verify signal VRF. In this case, control returns to step S5 to execute the erasure operation again. That is, at timing t4, as shown by (j) and (i) in FIG. 29, the internal signal D is set to "L" level and the internal signal C is set to "H" level, in quite the same way as the operation after the time t2.
After the re-erasure operation ends at time t5, the verify period starts again to check the perfect erasure operation beginning from the first. As the result of this check, when the erasure is imperfect, control returns to step S5 to execute the erasure and verify operation again. As the result of verify, when the erasure is perfect and the address reaches the final address in step S10, control determines that all the data in-the chip have been erased completely, so that the chip erasure operation ends.
Here, in the above-mentioned verify period, as far as the erasure is executed perfectly, the intervals of the address advance is about 2 microseconds.
In other words, assuming that the address advance operation (2 microseconds) is repeated by 10.sup.6 times; the erasure operation (10 ms) is repeated 100 times; and the verify result discrimination (3 microseconds) is repeated 100 times, it takes about 3 seconds to erase all the bits in this chip erasure mode.
The operation of when data of the cell array 1 are erased in unit of block (1 to 8) will be described hereinbelow with reference to a flowchart shown in FIG. 30 and a timing chart shown in FIG. 31. Here, in FIG. 31, (a) denotes the external voltage Vpp; (b) denotes the external OE signal; (c) denotes the control signal CME; (d) denotes the external CE signal; (e) denotes the timing at which data inputs Din1 to Din4 are inputted as commands; (f) denotes the block addresses AL*0 to AL*2; (g) denotes the status (level) of the data input Din1 to Din4; (h) denotes the internal signal A; (i) denotes the internal signal B; (j) denotes the status (level) change of the address AL*0, the inversion addresses/AL*1 and/AL*2; (k) denotes the status change of the inversion address /AL*0 and the address AL*1 and AL*2; (1) denotes the status of the block select line EA2; (m) denotes the status of the block select signal EA1 and EA3 to EA8; (n) denotes the internal signal C; (o) denotes the internal signal D; (p) denotes the verify signal VRF; (q) denotes the address A*0; (r) denotes the address A*1; (s) denotes the address A*n; (t) denotes the word select line WL1; (u) denotes the word select line WL2; (v) denotes the word select line WLn; (w) denotes the column decode signal h1; (x) denotes the column decode signal h2; (y) denotes the column decode signal g2; (z) denotes the column decode signal g1 and g3 to g8; (X) denotes the cell source line voltage of the cell array block 2 of the cell array 1; and (Y) denotes the cell source line voltage of the cell array blocks 1 and 3 to 8 of the cell array 1, respectively.
First, at time t1, simultaneously when the external voltage Vpp rises up to 12.5 V as shown by (a) in FIG. 31, the external OE signal changes to the "H" level as shown by (b). As a result, the control signal CME of the read/write control circuit 14 changes to the "H" level as shown by (c).
Then, command data are fed as the data inputs Din1 to Din4 from the input/output circuit 9 as shown by (e). In the case of the block erasure, these command data are "F", as shown in step S1 in FIG. 30.
In accompany with the input of the command data "F", the addresses A0 to A2 of the input addresses A0 to An are latched by the address latch circuit 4 as the block addresses A*0 to A*2, as shown by (f).
Then, the external CE signal is inputted as a negative signal, as shown by (d). When the external CE signal rises at time t2, control proceeds to step S2. At this time, the address latch circuit 4 latches the block addresses A*0 to A*2. The latched block addresses AL*0 to AL*2 are decoded by the block decoder 3 to select one of the block select signals EA1 to EA8. As a result, one of the cell source voltage supply blocks CSC1 to CSC8 of the cell source voltage supply circuit 2 is selected for erasure. In this example, as shown by (j) and (k), the block address AL*0 is "1" and the block addresses A*1 and A*2 are "0" Therefore, the block select signals EA1 to EA8 (the output of the block decoder 3) are as follows: the block select line EA2 is activated as shown by (1), and the block select lines EA3 to EA8 are deactivated as shown in by (m).
At time t2, when the command data "F" are latched by the command input circuit 12, the internal signals A and C of the command input circuit 12 change to the "H" level as shown by (h) and (n). At this time, the erasure operation starts in step S3 in FIG. 30.
In step S4, the counter circuit 10 is set by the automatic erase control circuit 13. As a result, in step S5, the internal addresses A*3 to A*n are zeroed as shown by (q), (r) and (s), so that the row decoder circuit 6 and the column decoder circuit 15 are both set to the nonselect status on the basis of the internal signal C.
In step S6, on the basis of the internal signal C, a voltage of 12 V is applied from one of the cell source voltage supply blocks CSC1 to CSC8 (in this example, the block CSC2) selected by the block select signals EA1 to EA8 to the cell source line of the corresponding one (the second block) of the cell array blocks 1 to 8 of the cell array 1, as shown by (X). Further, no erase voltage is applied to the other cell array blocks 1 to 8, as shown by (Y). As a result, only one of the block of the cell array blocks 1 to 8 is erased in step S4. In this erasure operation, the erasure period is bout 10 ms.
When the erasure period ends at time t3, the internal signal C returns to the "L" level as shown by (n), and the internal signal D returns to the "H" level as shown by (o), so that the verify period starts. In this case, in step S7, the cell source voltage applied by the cell source voltage supply block CSC2 of the cell source voltage supply circuit 2 is set to 0 V to stop erasure operation as shown by (X).
In the verify period, the internal addresses A*3 to A*n are advanced by the counter circuit 10 to execute the verify in step S8 and the data "1" check in step S10, by reading data from the selected block. In this case, the addresses A*3 to A*n are incremented as shown by (q), (r) and (s); the word select lines WL1 to WLn change as shown by (t), (u) and (v); and the column select signals h1 and h2 change as shown by (w) and (x). Here, with respect to the addresses A*0 to A*2, since the block address AL*0 is "1" and the block addresses A*1 and A*2 are "0", the column decode signal g2 changes to the "H" level as shown by (y), and the column decode signals g1 and g3 to g8 are kept unchanged at the "L" level as shown by (z). As far as the erasure is executed perfectly at the respective addresses, since the data D*1 to D*4 read through the sense amplifier 8 are all "1", the verify circuit 11 outputs the verify signal VRF as shown by (p). The outputted verify signal VRF is given to the counter circuit 10. Here, when the address of the counter circuit 10 is not the final address, control proceeds from step S11 to step S9 to increment the count value of the counter circuit 10, so that the address is advanced by 1. As a result, data at the succeeding address are read through the sense amplifier 8, and the read data are also verified.
Now, as the result of the data check in step S8, the erasure is not sufficient, the verify circuit 11 does not output the verify signal VRF. In this case, control returns to step S6 to execute the erasure operation again. That is, at timing t4, the internal signal D is set to the "L" level as shown by (o) and the internal signal C is set to "H" level as shown by (n), in quite the same way as the operation after the time t2.
After the re-erasure operation ends at time t5, the verify period starts again to check the perfect erasure beginning from the first address of the block. As the result of verify, when the erasure is perfect and the address reaches the final address in step S11, the operation ends.
Here, in the above-mentioned verify period, as far as the erasure operation is executed perfectly, the intervals of the address advance is about 2 microseconds.
In other words, assuming that the address advance operation (2 microseconds) is repeated by 1.28.times.10.sup.5 times; the erasure (10 ms) is repeated 100 times; and the verify result discrimination (3 microseconds) is repeated 100 times, it takes about 1.25 seconds to erase all the bits of the block to be erased.
In the prior art non-volatile semiconductor memory device as described above, the chip erasure and the block erasure can be selectively executed. Accordingly, in the chip test, it is necessary to check each of these functions. In the case of the block erasure, however, it takes about 1.25 seconds to check only one block. Therefore, it takes about 10 second to check all the blocks (because 8 blocks in this embodiment). This time required for semiconductor device check is relatively long, which cannot be neglected when the memory of large capacity is manufactured in the future. Therefore, there exists a need of shortening the test time for confirming the block erasure function of the memory chip, from the standpoint of cost reduction.